1. Field of the Invention
The invention relates generally to phase locked loop circuits, and more particularly to systems and methods for initializing these circuits and measuring the characteristics of voltage controlled oscillators within the circuits.
2. Related Art
A phase-locked loop circuit, or PLL, is electronic circuit that is designed to control an oscillator to produce a signal that is locked onto a reference signal. In other words, the signal produced by the oscillator is kept in phase with the reference signal. The oscillator signal may have the same frequency as that reference signal, or it may be a multiple or fraction of the reference signal.
Referring to FIG. 1, the structure of an exemplary circuit in accordance with the prior art is shown. PLL circuit 100 includes a phase frequency detector 110, a charge pump 120, a voltage controlled oscillator 130, a divider 140 and a capacitor 150. PLL circuit 100 receives a reference clock signal, REF_CLK, and generates an output signal, PLL_OUT, which in this case is also a clock signal. The frequency of PLL_OUT is a multiple of REF_CLK, as determined by divider 140. This will be explained more detail below.
It can be seen from FIG. 1 that phase frequency detector 110 receives the reference clock signal, REF_CLK, as well as a feedback clock signal, FB_CLK. Phase frequency detector 110 compares these two signals and determines whether the frequency of the feedback clock signal is higher or lower than the reference clock signal. If the frequency of the feedback clock signal is higher than the frequency of the reference clock signal, phase frequency detector 110 asserts a “down” signal, DN. If, on the other hand, the frequency of the feedback clock signal is lower than the frequency of the reference clock signal, phase frequency detector 110 asserts a “up” signal, UP.
The UP and DN signals generated by phase frequency detector 110 are provided to charge pump 120. These signals are used by charge pump 120 to control a current source and a current drain within the charge pump. If the UP signal is asserted, charge pump 120 couples the current source to its output. If the DN signal is asserted, charge pump 120 couples the current drain to its output. Thus, depending upon whether UP or DN is asserted, the output of charge pump 120 effectively acts as a current source or a current drain.
The output of charge pump 120 is coupled to the input of voltage controlled oscillator 130. The connection between charge pump 120 and voltage controlled oscillator 130 is a node that is sometimes referred to as the voltage control node (VC). This node is called the voltage control node because it is the voltage at this node that controls the frequency of the oscillations produced by voltage controlled oscillator 130. By alternately coupling the voltage control node to a current source or a current drain, the charge (and corresponding voltage) at the node can be controlled, thereby controlling the frequency of oscillations produced by voltage controlled oscillator 130 (i.e., the output of PLL circuit 100.)
Because the frequency of voltage controlled oscillator 130 is dependent upon the voltage at the voltage control node, PLL circuit 100 is typically very sensitive to changes in the voltage at this node. The voltage control node is therefore coupled to ground through capacitor 150. This serves to shunt oscillations in the voltage at the node (particularly high frequencies) to ground, stabilizing the voltage at the node. This, in turn, stabilizes the frequency of oscillations produced by voltage controlled oscillator 130.
While the design of PLL circuit 100 is adequate for some implementations, it would be helpful to provide additional features that would make the PLL more useful. For example, it is generally useful to have a characterization of the PLL. In other words, it is useful to know the correspondence between the voltage at the voltage control node and the frequency of the output signal. This process, while straightforward, can be very time-consuming in a laboratory environment. In a manufacturing environment, the difficulty of characterizing the PLL can be prohibitive. As an alternative to characterizing the entire PLL, it may be useful to simply determine the frequency-versus-voltage characteristics of the voltage controlled oscillator. This information can provide an alternative means for determining whether the PLL circuit will operate properly through the range of possible voltages/frequencies.
Conventionally, however, this information is obtained by coupling circuitry to the voltage control node to control the voltage at the node. This voltage can then be varied (e.g., stepped) across a range of voltages, and the corresponding frequencies produced by the voltage controlled oscillator can be measured. This data can then be plotted to show the frequency-versus-voltage characteristics of the voltage controlled oscillator. One of the problems with this approach, however, is that the additional circuitry creates noise at the voltage control node and thereby degrades the performance of the PLL circuit.
Another desirable feature relates to the initialization of the PLL circuit. When the circuit is powered on, the voltage at the voltage control node is unknown. The voltage may be anywhere between a minimum voltage (e.g., ground) to a maximum voltage (e.g., Vdd.) This can be a problem because, if the voltage is at its maximum value, the signal generated by voltage controlled oscillator 130 will be at its maximum frequency. The components of PLL circuit 100 must therefore be designed to operate correctly, even if the voltage at the voltage control node and the frequency of the signal produced by voltage controlled oscillator 130 are at their maximum values. Otherwise, PLL circuit 100 may not lock (i.e., it may malfunction.) Because it is generally more difficult to design high-performance components, such as divider 140, to handle the higher voltages and frequencies, this may increase the difficulty, complexity and/or cost of designing the components and the circuit.
Conventional PLL circuit designs sometimes include a mechanism coupled to the voltage control node to pull down the voltage at the node when the circuit is initialized. For example, in some conventional designs, the voltage control node is coupled to ground through a transistor that is switched on and off by an initialization signal. When the circuit is being initialized, the transistor is switched on to couple the voltage control node to ground and thereby pull down the voltage. After the circuit is initialized, the transistor is switched off to decouple the voltage control node from ground. While this mechanism is effective to prevent the circuit from initializing at a high-frequency, it also has the disadvantage of introducing noise at the voltage control node.
It would therefore be desirable to provide systems and/or methods for providing these features without the disadvantages that are inherent in the conventional means for providing these features.